经历
- (摩尔多瓦)基尔尼乔夫国立大学应用数学学士(现摩尔多瓦国立大学),丰桥技术科学大学大学院工学研究科硕士课程修完了(信息工学专业),大阪大学大学院基础工学研究科博士后期课程修完了(工学博士),丰桥技术科学大学名誉博士
- 原河内国家大学工科大学(VNU-UET)校长,原河内国家大学国际法语圈研究所所长(VNU-IFI),原河内理工大学图书馆信息网络中心(HUT-LINC) 主任
- ACM/IEEE,电子信息通信学会(IEICE),越南信息处理学会(VAIP),越南电子通信学会(REV),原信息通信研究机构(NICT)国际顾问委员会,原越南电子通信学会会长
- 原“ 越南原日本留学生协会 ”会长,原“ASEAN 原日本留学生评议会 (ASCOJA)”会长,原ASJA International( 日本外务省 ) 理事,原越日友好协会副会长
- 京都情报大学院大学副校长
担当科目
- 软件工程
- 信息伦理特论
- 优等生论文
专业领域
- 嵌入式系统协同设计优化方法
- 软件工程
- 知识科学(数据科学、人工智能、大数据、KDD&DM)
成果
- C.T.M.Hue,D.D.Hanh,and N.N.Binh:“USLTG: A Test Case Automatic Generation by Transforming Use Cases,” Int’l Journal of Software Engineering and Knowledge Engineering Journal IJSEKE, 2019. ISSN (online): 1793-6403 (Accepted, ISI indexed).
- C.T.M.Hue,D.D.Hanh,N.N.Binh,and L.M. Duc:“USL: A Domain-Specific Language for Precise Specification of Use Cases and Its Transformations,”Int’l journal Informatica,Vol 42(3), pp. 323-343, 2018. ISSN 0350-5596. (Scopus indexed)
- N.N.Binh: “Instruction Set Optimization for ASIP Design,” VNU Publisher, Hanoi, 2017, June 2017 (ISBN: 978-604-934-862-4)
- T.N.Phu, N.Q. Dzung, L.V. Hoang, and N.N. Binh: “Towards Malware Detection in Routers with C500-toolkit,” Proc. of the ICoICT 2017 Conference, Malaysia, 17-19 May 2017.
- N.N.Binh, P.V. Huong, and B.N. Hai: “A New Approach to Embedded Software Optimization based on Reverse Engineering,” IEICE Trans. on Information and Systems, Vol.E98-D, No.6, pp. 1166-1175, June 2015.
- N.N.Binh: “Embedded Software Engineering,” VNU Publisher, Hanoi, 2014 (Textbook)
- P.V.Huong, N.N. Binh, and P.N. Thanh: “Optimizing Occupied Memory of Embedded Software in the Design Phase,” Journal of Computer Science and Cybernetics, V.28, N.3, pp. 234-244, 2012.
- P.V.Huong and N.N. Binh: ”Design and Generating Code for Embedded Systems Based on DSL and T4,” Journal of Computer Science and Cybernetics, V.28, N.4, pp. 323-332, 2012.
- P.V.Huong and N.N. Binh: “Embedded System Architecture Design and Optimization at the Model Level,” Int’l Journal of Computer and Communication Engineering (IJCCE), Vol. 1, No. 4, pp. 345-349, Nov. 2012. (ISSN: 2010-3743).
- Ho,T.B., Kawasaki, S., and Nguyen, N.B. (N.N. Binh): “Cluster-based Information Retrieval with Tolerance Rough Set Model,” Int’l Journal of Fuzzy Logic and Intelligent System, pp. 26-32, Vol. 1. Extension of the paper in Proc. of the 2nd Int’l Symposium on Advanced Intelligent Systems, pp. 6-11. Korea, Aug. 2001.
- Ho,T.B. and Nguyen, N.B. (N.N. Binh): “Document Clustering by Tolerance Rough Set Model,” Int’l Journal of Intelligent Systems, pp. 199-212, Vol.17. John Wiley & Sons, Inc., 2002.
- N.N.Binh, M. Imai, and Y. Takeuchi: “A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes,” Proc. of ASP-DAC'98, pp. 367-372, Yokohama, Japan, Feb. 1998.
- N.N.Binh, M. Imai, and Y. Takeuchi: “An Optimization Algorithm for High Performance ASIP Design with Considering the RAM and ROM Sizes,” IEICE Trans. Fundamentals, Vol.E81-A, No.12, pp.2612 - 2620, Dec. 1998.
- N.N.Binh, M. Imai, A. Shiomi, and N. Hikichi: “A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts,” Proc. of the 33rd IEEE/ACM Design Automation Conference (DAC'96), pp. 527-532, Las Vegas, USA, Jun. 1996.
- N.N.Binh, M. Imai, A. Shiomi, and N. Hikichi: “Optimal Instruction Set Design through Adaptive Database Generation,” IEICE Trans. Fundamentals, Vol. E79-A, No.3, pp. 347 - 353, Mar. 1996.
- N.N.Binh, M. Imai, A. Shiomi, N. Hikichi, Y. Honma, and J. Sato: “An Efficient Scheduling Algorithm for Pipelined Instruction Set Processor and Its Application to ASIP Hardware/Software Codesign,” IEICE Trans. Fundamentals, Vol.E78-A, No.3, pp. 353-362, Mar. 1995.
- N.N.Binh, M. Imai, A. Shiomi, and N. Hikichi: “An Instruction Set Optimization Algorithm for Pipelined ASIPs,” IEICE Trans. Fundamentals, Vol.E78-A, No.12, pp. 1707-1714, Dec.1995.
获奖情况
- 获得电子信息通信学会优秀研究结果奖(东海分会)
- 日本外务省奖
- 大阪大学Global Alumni Fellow